Set/reset algorithm which detects and repairs weak cells in resistive-switching memory device

ABSTRACT

A resistance-switching memory cell is programmed in a set or reset operation which tests the stability of the cell. A first programming phase using program voltages which increase in magnitude or duration until a program verify test is passed. A stability test phase is then performed to evaluate a stability of the memory cell. The stability test phase determines whether the memory cell is weak and likely to transition out of the set or reset state by applying one or more disturb pulses and performing one or more stability verify tests. The disturb pulses can have a reduced magnitude or duration compared to the program voltages. If the stability test phase indicates the memory cell is not stable, a second programming phase is performed. If the stability test phase indicates the memory cell is stable, the operation is concluded.

BACKGROUND

The present technology relates to data storage.

A variety of materials show resistance-change or resistance-switchingbehavior in which the resistance of the material is a function of thehistory of the current through, and/or voltage across, the material.These materials include chalcogenides, carbon polymers, perovskites, andcertain metal oxides (MeOx) and metal nitrides (MeN). Specifically,there are metal oxides and nitrides which include only one metal andexhibit reliable resistance switching behavior. This group includes, forexample, Nickel Oxide (NiO), Niobium Oxide (Nb2O5), Titanium Dioxide(TiO2), Hafnium Oxide (HfO2) Aluminum Oxide (Al2O3), Magnesium Oxide(MgOx), Chromium Dioxide (CrO2), Vanadium Oxide (VO), Boron Nitride(BN), and Aluminum Nitride (AlN). The material may be formed in aninitial state, for example, a relatively low-resistance state. Uponapplication of sufficient voltage, the material switches to a stablehigh-resistance state which is maintained after the voltage is removed.In some cases, the resistance switching is reversible such thatsubsequent application of an appropriate current or voltage can serve toreturn the material to a stable low-resistance state which is maintainedafter the voltage or current is removed. This conversion can be repeatedmany times. For some materials, the initial state is high-resistancerather than low-resistance. A set process may refer to switching thematerial from high to low resistance, while a reset process may refer toswitching the material from low to high resistance. The set and resetprocesses can be considered to be programming processes which change theresistance state. In other cases, the resistance switching isirreversible.

Resistance-change materials are of interest for use in nonvolatilememory arrays. One resistance state may correspond to a data “0,” forexample, while the other resistance state corresponds to a data “1.”Some of these materials may have more than two stable resistance states.Moreover, in a memory cell, the material can be in series with asteering element such as a diode, which selectively limits the voltageacross, and/or the current flow through, the material. For example, adiode can allow current to flow in only one direction of the whileessentially preventing a current flow in the opposite direction. Such asteering element itself is not typically a resistance-change material.Instead, the steering element allows a memory cell to be written to,and/or read from, without affecting the state of other memory cells inan array.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified perspective view of one embodiment of a memorycell which includes a resistance-switching material in series with asteering element.

FIG. 2A is a simplified perspective view of a portion of a first memorylevel formed from a plurality of the memory cells of FIG. 1.

FIG. 2B is a simplified perspective view of a portion of athree-dimensional memory array formed from a plurality of the memorycells of FIG. 1.

FIG. 2C is a simplified perspective view of a portion of a monolithicthree-dimensional array 122 that includes a first memory level 128positioned below a second memory level 129, where the upper conductors131 of the first memory level are used as the lower conductors of thesecond memory level.

FIG. 3 is a block diagram of one embodiment of a memory system.

FIG. 4A is a graph depicting I-V characteristics of an example bipolarresistance-switching material which sets using a positive voltage.

FIG. 4B is a graph depicting I-V characteristics of an example bipolarresistance-switching material which sets using a negative voltage.

FIG. 4C1 depicts a portion of the I-V plots of FIG. 4A or 4B showing theuse of a verify voltage of a stability verify test (Vver_stability)which is less than a verify voltage (Vread) of a program verify test, tomake the stability verify test more strict than the program verify testin a set process.

FIG. 4C2 depicts a portion of the I-V plots of FIG. 4A or 4B showing theuse of a verify voltage of a stability verify test (Vver_stability)which is more than a verify voltage (Vread) of a program verify test, tomake the stability verify test less strict than the program verify testin a set process.

FIG. 4D depicts a portion of the I-V plots of FIG. 4A or 4B showing theuse of a verify current of a stability verify test (Iverify_set+ΔI)which is more than a verify current of a program verify test(Iverify_set), to make the stability verify test more strict than theprogram verify test in a set process, or the use of a verify current ofa stability verify test (Iverify_set−ΔI) which is less than a verifycurrent of a program verify test (Iverify_set), to make the stabilityverify test less strict than the program verify test in a set process.

FIG. 4E1 depicts a portion of the I-V plots of FIG. 4A or 4B showing theuse of a verify voltage of a stability verify test (Vver_stability)which is more than a verify voltage (Vread) of a program verify test, tomake the stability verify test more strict than the program verify testin a reset process.

FIG. 4E2 depicts a portion of the I-V plots of FIG. 4A or 4B showing theuse of a verify voltage of a stability verify test (Vver_stability)which is less than a verify voltage (Vread) of a program verify test, tomake the stability verify test less strict than the program verify testin a reset process.

FIG. 4F depicts a portion of the I-V plots of FIG. 4A or 4B showing theuse of a verify current of a stability verify test (Iverify_reset−ΔI)which is less than a verify current of a program verify test(Iverify_reset), to make the stability verify test more strict than theprogram verify test in a reset process, or the use of a verify currentof a stability verify test (Iverify_reset+ΔI) which is more than averify current of a program verify test (Iverify_set), to make thestability verify test less strict than the program verify test in areset process.

FIG. 5 depicts an embodiment of a circuit for reading the state of amemory cell.

FIG. 6A depicts an example process for changing the resistance state ofa memory cell.

FIG. 6B depicts example details of a first programming phase inaccordance with step 601 of FIG. 6A.

FIG. 6C depicts example details of a stability test phase in accordancewith step 602 of FIG. 6A.

FIG. 6D depicts alternative example details of a stability test phase inaccordance with step 602 of FIG. 6A.

FIG. 6E depicts example details of a second programming phase inaccordance with step 603 of FIG. 6A.

FIG. 6F depicts a comparative set operation which is concluded after aprogram verify test is passed.

FIG. 6G depicts a comparative reset operation which is concluded after aprogram verify test is passed.

FIG. 6H depicts a relaxation of resistance-switching memory cells fromthe set or reset state over a time period such as one minute.

FIG. 7 depicts example voltages used in a set process, where a magnitudeof the program voltages increases in first and second programmingphases, two disturb voltages have a same polarity as the programvoltages and a read operation is performed after each of the two disturbvoltages.

FIG. 8 depicts example voltages used in a set process, where a magnitudeof the program voltages increases in first and second programmingphases, three disturb voltages have a same polarity as the programvoltages and a read operation is performed after the three disturbvoltages.

FIG. 9 depicts example voltages used in a set process, where a magnitudeof the program voltages increases in first and second programmingphases, two disturb voltages have a same polarity as the programvoltages and a read operation is performed after each of the two disturbvoltages.

FIG. 10 depicts example voltages used in a set process, where amagnitude of the program voltages increases in first and secondprogramming phases, two disturb voltages have an opposite polarity asthe program voltages and a read operation is performed after the twodisturb voltages.

FIG. 11 depicts example voltages used in a set process, where amagnitude of the program voltages increases in first and secondprogramming phases, two disturb voltages have different polarities and aread operation is performed after the two disturb voltages.

FIG. 12 depicts example voltages used in a set process, where amagnitude of the program voltages increases in first and secondprogramming phases, and two disturb voltages are additional programvoltages.

FIG. 13 depicts example voltages used in a reset process, where amagnitude of the program voltages increases in first and secondprogramming phases, two disturb voltages have a same polarity as theprogram voltages and a read operation is performed after the two disturbvoltages.

DETAILED DESCRIPTION

A programming technique is provided for improving the stability of aresistance-switching memory device. The technique detects and fixes weakmemory cells which are likely to relax from their programmed state.Moreover, these weak memory cells can be detected and fixed quicklywithout degrading other memory cells which are stable in a programmedstate.

To allow memory devices to be scaled to smaller dimensions, operatingcurrents are reduced. However, this can degrade the stability of a highor low resistance state in a resistance-switching memory cell. Forexample, resistance-switching materials such as metal oxides which areoperated at a low current such as less than 20 μA can experience anunstable resistance state. That is, the resistance state which isreached after a set/reset operation at low current may change backtoward its original state in a short time in a process referred to as“cell relaxation.” This is a significant reliability issue. In contrast,when a memory cell is set/reset at a higher power (with acorrespondingly higher current, e.g., >40 uA) a more stable state can beachieved. In this case, the memory cell is operated at lower resistancestate, e.g., having an on resistance of R_on <100 KOhm. However, asmentioned, the higher operating current limits the ability to scale thememory device to smaller dimensions. Also, high current limits thenumber of bits to be programmed at the same time, resulting in a lowspeed product. Similarly, a longer set/reset time (e.g., a programvoltage duration in the millisecond range) can be used to obtain a morestable state. However, this long duration reduces device performance interms of speed.

Programming techniques provided herein address these challenges. In oneapproach, in a set or reset process, a memory cell is programmed in afirst programming phase until a program verify test is passed. Astability test phase then tests the stability of the memory cell, e.g.,the likelihood that the memory cell will relax by transitioning out ofthe programmed state. In one implementation, the stability test phaseapplies one or more voltages which are less intense than the voltagesapplied during the first programming phase to perturb the memory cellwithout programming it further. For example, the stability test phasecan apply disturb voltages have a reduced duration and/or magnitudecompared with regular program voltages of a set/reset operation.

The stability test phase can apply a stability verify test after the oneor more voltages to assess how the memory cell has responded to theperturbations. The stability verify test can be the same or differentthan the program verify test. If the result of the stability test phaseindicates that the memory cell has relaxed out of the programmed state,a second programming phase is performed in which one or more additionalprogram voltages are applied. These voltages can be applied with acharacteristic such as amplitude, duration or current limit which isbased on a value of the characteristic at a conclusion of the firstprogramming phase. If the result of the stability test phase indicatesthat the memory cell has not relaxed out of the programmed state, theprogramming operation can be concluded without the second programmingphase. A memory cell which has a stable state can sustain the disturbvoltages. Thus, a set or reset is considered to be completed when thememory cell passes one or more stability verify tests after reaching atarget verify level in a first programming phase.

A number of variations exist regarding the disturb voltages. Forexample, the polarity of all of the disturb voltages can be the same asthe polarity of the program voltages. Or, the polarity of all of thedisturb voltages can be opposite to the polarity of the programvoltages. In another approach, both opposite and same polarity voltagesare used. As an example, one to five disturb voltages can be used. Insome implementations, the voltage amplitude is 20% to 100% of theamplitude of the program voltages.

FIG. 1 is a simplified perspective view of one embodiment of a memorycell which includes a resistance-switching material in series with asteering element. The memory cell 100 is between a first conductor 106and a second conductor 108 and includes a top electrode 132, aresistance-switching material 130 and a bottom electrode 134. The memorycell also includes a steering element 104 such as a diode comprising aheavily doped n+ polysilicon region 142, a lightly doped or an intrinsic(unintentionally doped) polysilicon region 144 above the n+ polysiliconregion 142 and a heavily doped p+ polysilicon region 146 above theintrinsic region 144. An optional adhesion or barrier layer 113 may beincluded on top of the conductor 106.

As mentioned, a resistance-switching material has a resistivity that maybe reversibly switched between two or more states. For example, thematerial may be in an initial high-resistivity (high resistance) stateupon fabrication that is switchable to a low-resistivity state uponapplication of a first voltage and/or current. Application of a secondvoltage and/or current may return the material to the high-resistivitystate. Alternatively, the material may be in an initial low-resistancestate upon fabrication that is reversibly switchable to ahigh-resistance state upon application of the appropriate voltage(s)and/or current(s). When used in a memory cell, one resistance state forthe material may represent a binary “0” while another resistance statemay represent a binary “1.” In some case, more than two data/resistancestates may be used.

In one embodiment, the process of switching the resistance-switchingmaterial from the high-resistivity state (representing, e.g., binarydata “0”) to the low-resistivity state (representing, e.g., binary data“1”) is referred to as setting or forming, and the process of switchingthe resistance-switching material from the low-resistivity state to thehigh-resistivity state is referred to as resetting. In otherembodiments, setting and resetting and/or the data encoding can bereversed. The set or reset process can be performed for a memory cell toprogram it to a desired state to represent binary data.

The conductors 106 and 108 may be control lines such as a bit line or aword line. In one embodiment, the top electrode 132 is made of titanium(Ti) or titanium nitride (TiN). The bottom electrode may be made ofTitanium Nitride (TiN), and serves as an adhesion and barrier layer.

The steering element 104 can be a diode, as mentioned, or other suitablesteering element that exhibits non-ohmic conduction by selectivelylimiting the voltage across and/or the current flow through theresistance-switching material. In one approach, the steering elementallows current to flow through the resistance-switching material in onlyone direction, e.g., from the bit line to the word line. In anotherapproach, a steering element such as a punch-through diode allowscurrent to flow through the resistance-switching material in eitherdirection depending on the polarity and voltage applied.

In this manner, the memory cell may be used as part of a two- orthree-dimensional memory array and data may be written to and/or readfrom the memory cell without affecting the state of other memory cellsin the array.

The steering element and the resistance-switching material together canbe in the shape of a vertical pillar.

Conductors 106 and 108 include any suitable conductive material such astungsten, any appropriate metal, heavily doped semiconductor material, aconductive silicide, a conductive silicide-germanide, a conductivegermanide, or the like. In the embodiment shown, the conductors 106 and108 are rail-shaped and extend in different directions (e.g.,substantially perpendicular to one another). Other conductor shapesand/or configurations may be used. In some embodiments, barrier layers,adhesion layers, antireflection coatings and/or the like (not shown) maybe used with conductors 106 and 108 to improve device performance and/oraid in device fabrication. The conductors 106 may be a word line whilethe conductor 108 is a bit line, or vice-versa.

In an example implementation, the top electrode 132 and the bottomelectrode 134 are a conductive material such as n+Si, while theresistance-switching materials 130 is HfOx.

While the resistance-switching material 130 is shown as being positionedabove the steering element 104, in alternative embodiments, theresistance-switching material may be positioned below the steeringelement 104. Various other configurations are possible as well. Aresistance-switching material can exhibit unipolar or bipolarresistance-switching characteristics. With a unipolarresistance-switching characteristic, the voltages used for both set andreset processes are of the same polarity, i.e., either both positive orboth negative. In contrast, with a bipolar resistance-switchingcharacteristic, opposite polarity voltages are used for the set andreset processes. Specifically, the voltage used for the set process canbe positive while the voltage used for the reset process is negative, orthe voltage used for the set process can be negative while the voltageused for the reset process is positive.

FIG. 2A is a simplified perspective view of a portion of a first memorylevel 114 formed from a plurality of the memory cells 100 of FIG. 1. Forsimplicity, the resistance-switching material and the steering elementare not separately shown. The memory array 114 is a “cross-point” arrayincluding a plurality of bit lines (second conductors 108) and wordlines (first conductors 106) to which multiple memory cells are coupledas shown. Other memory array configurations may be used, as may multiplelevels of memory.

FIG. 2B is a simplified perspective view of a portion of a monolithicthree-dimensional array 116 that includes a first memory level 118positioned below a second memory level 120. Each memory level includes aplurality of memory cells 100 in a cross-point array. Additional layers(e.g., an inter-level dielectric) may be present between the first andsecond memory levels but are not shown for simplicity. Other memoryarray configurations may be used, as may additional levels of memory. Inthe embodiment of FIG. 2B, all diodes may “point” in the same direction,such as upward or downward depending on whether p-i-n diodes having ap-doped region on the bottom or top of the diode are employed,simplifying diode fabrication.

FIG. 2C is a simplified perspective view of a portion of a monolithicthree-dimensional array 122 that includes a first memory level 128positioned below a second memory level 129, where the upper conductors131 of the first memory level are used as the lower conductors of thesecond memory level. In such embodiments, the diodes on adjacent memorylevels can point in opposite directions. For example, the diodes of thefirst memory level may be upward pointing diodes as indicated by arrowA1 (e.g., with p regions at the bottom of the diodes), while the diodesof the second memory level may be downward pointing diodes as indicatedby arrow A2 (e.g., with n regions at the bottom of the diodes), or viceversa.

A monolithic three-dimensional memory array is one in which multiplememory levels are formed above a single substrate, such as a wafer, withno intervening substrates. The layers forming one memory level aredeposited or grown directly over the layers of an existing level orlevels. In contrast, stacked memories have been constructed by formingmemory levels on separate substrates and adhering the memory levels atopeach other.

The above examples show memory cells in a cylindrical or pillar shapeand conductors in the shapes of rails according to the disclosedarrangements. However, the technology described herein is not limited toany one specific structure for a memory cell. Other structures can alsobe used to form memory cells that include resistance-switchingmaterials. Another example memory configuration is a vertical bit linecross point memory array such as described in U.S. pat. app. pub.2012/0147648, published Jun. 14, 2012 and titled “Three DimensionalNon-Volatile Storage With Dual Gate Selection Of Vertical Bit Lines.”

FIG. 3 is a block diagram that depicts one example of a memory system300 that can implement the technology described herein. Memory system300 includes a memory array 302 that can be a two- or three-dimensionalarray of memory cells as described above. In one embodiment, memoryarray 302 is a monolithic three-dimensional memory array. The arrayterminal lines of memory array 302 include the various layer(s) of wordlines organized as rows, and the various layer(s) of bit lines organizedas columns. However, other orientations can also be implemented.

Memory system 300 includes row control circuitry 320, whose outputs 308are connected to respective word lines of the memory array 302. Rowcontrol circuitry 320 receives a group of M row address signals and oneor more various control signals from system control logic circuit 330,and typically may include such circuits as row decoders 322, arrayterminal drivers 324, and block select circuitry 326 for both read andprogramming (e.g., set and reset) operations. Memory system 300 alsoincludes column control circuitry 310 whose input/outputs 306 areconnected to respective bit lines of the memory array 302. Columncontrol circuitry 310 receives a group of N column address signals andone or more various control signals from system control logic 330, andtypically may include such circuits as column decoders 312, arrayterminal receivers or drivers 314, block select circuitry 316, as wellas read/write circuitry, including sense amps and I/O multiplexers.System control logic 330 receives data and commands from a host andprovides output data to the host. In other embodiments, system controllogic 330 receives data and commands from a separate controller circuitand provides output data to that controller circuit, with the controllercircuit communicating with the host. System control logic 330 mayinclude one or more state machines, registers and other control logicfor controlling the operation of memory system 300. For example, writecircuitry 560, sense amplifier 566 and clamp control circuitry 564,discussed further below in FIG. 5, may be provided.

In one embodiment, all of the components depicted in FIG. 3 are arrangedon a single integrated circuit or chip. For example, system controllogic 330, column control circuitry 310 and row control circuitry 320can be formed on the surface of a substrate and memory array 302 in amonolithic three-dimensional memory array formed above the substrate(and, therefore, above system control logic 330, column controlcircuitry 310 and row control circuitry 320). In some cases, a portionof the control circuitry can be formed on the same layers as some of thememory array.

Integrated circuits incorporating a memory array usually subdivide thearray into a number of sub-arrays or blocks. Blocks can be furthergrouped together into bays that contain, for example, 16, 32, or adifferent number of blocks. As frequently used, a sub-array is acontiguous group of memory cells having contiguous word and bit linesgenerally unbroken by decoders, drivers, sense amplifiers, andinput/output circuits. This is done for any of a variety of reasons. Forexample, the signal delays traversing down word lines and bit lineswhich arise from the resistance and the capacitance of such lines (i.e.,the RC delays) may be very significant in a large array. These RC delaysmay be reduced by subdividing a larger array into a group of smallersub-arrays so that the length of each word line and/or each bit line isreduced. As another example, the power associated with accessing a groupof memory cells may dictate an upper limit to the number of memory cellswhich may be accessed simultaneously during a given memory cycle.Consequently, a large memory array is frequently subdivided into smallersub-arrays to decrease the number of memory cells which aresimultaneously accessed. Nonetheless, for ease of description, an arraymay also be used synonymously with sub-array to refer to a contiguousgroup of memory cells having contiguous word and bit lines generallyunbroken by decoders, drivers, sense amplifiers, and input/outputcircuits. An integrated circuit may include one or more than one memoryarray.

As described above, resistance-switching material may be reversiblyswitched between two or more states. For example, theresistance-switching material may be in an initial, high-resistivitystate upon fabrication that is switchable to a low-resistivity stateupon application of a first voltage and/or current. Application of asecond voltage and/or current may return the resistance-switchingmaterial to a high-resistivity state. The memory system 300 can usedwith any type of resistance-switching material.

FIG. 4A is a graph depicting I-V characteristics of an example bipolarresistance-switching material which sets using a positive voltage. Inthis example, the set process (a transition from Rhigh to Rlow) occurswhen a positive voltage is applied, and the reset process (a transitionfrom Rlow to Rhigh) occurs when a negative voltage is applied. Line 402represents the I-V characteristic when in the high-resistivity (Rhigh)state and line 400 represents a transition to the low-resistivity (Rlow)state. Line 401 represents the set process and line 403 represents thereset process.

A read voltage Vread is also depicted. To determine theresistance-switching material's state, Vread is applied across theresistance-switching material while the resulting current is measuredand compared to a reference or trip current Iread. A higher or lowermeasured current indicates that the resistance-switching material is inthe low- or high-resistivity state, respectively. For example, ifIoff<Iread is measured, the material is in the high resistance state. IfIon>Iread is measured, the material is in the low resistance state. Aforming voltage Vf is also depicted. This is an example of a user readwhich occurs after the memory cell has been programmed. In this case,the reference current is positioned to provide a roughly equal marginbetween the expected current in the Rlow state, Ion and the expectedcurrent in the Rhigh state, Ioff. Vread can also be used during aprogram verify process in which case the reference current can bedifferent than during a user read. For example, a set verify current(Iverify_set) can be greater than Iread to provide a margin above Iread.Similarly, a reset verify current (Iverify_reset) can be less than Ireadto provide a margin below Iread. Vread can be the same or differentduring a user read or a program verify read.

Specifically, due to sensing noise, temperature differences, supplyvoltage variation, cell relaxation variations and other factors, a givencell may not flow the exact same current when read at different times,e.g., verify versus user read. To ensure a valid user read with highprobability, the on chip circuitry can provide a margin between theverify read and the user read. The margin can be in the direction tomake it more difficult to pass a verify read than a user read. Forexample, if the cell is in a high current state (low resistance state)the verify read can be at a lower Vread, e.g., 50 mV lower, or with ahigher reference current as compared to user read conditions. For a cellin a low current state (high resistance state) the verify read can be ata slightly higher Vread or a lower reference current compared to userread conditions. See FIGS. 4C1 to 4F for examples of how changing thereference current or the applied voltage affects the sensing process.

Further, a stability verify test as discussed further below can useVread or another voltage level. A stability verify test can have thesame or different strictness compared to a program verify test. Oneapproach is to have a common reference current and read voltage for thestability verify test and the program verify test. Thus, there is acommon trip level for both cases. Further, there could be margin betweenthis common trip level for verify and the trip level for a user read.This approach results in a high probability of valid cell read. But,there is a higher probability of failing the stability verify test whennoise or very small relaxations occur. This results in a performancepenalty due to more frequency use of the second programming phase.

Another approach is for the stability verify test to be less strict thanthe program verify test. See FIG. 4C2, 4D, 4E2 and 4F. In this case,there is a margin between the program verify test and the stabilityverify test such that it is easier to pass the stability verify test.This approach reduces the probability of failing the stability verifytest, thereby also reducing the frequency with which the secondprogramming phase is used.

Yet another approach is for the stability verify test to be more strictthan the program verify test. See FIG. 4C1, 4D, 4E1 and 4F. Thisapproach increases the probability of failing the stability verify test,thereby also increasing the frequency with which the second programmingphase is used. However, this approach ensures that the cells are wellprogrammed so that the likelihood of relaxation is reduced.

A current limit Iset_limit for a current through the memory cell can beenforced during a set process.

During a set process, the program voltage Vpgm_set can have a range ofmagnitudes as indicated by arrow 405. The magnitude may be less thanVset and then step up. Similarly, during a reset process, the programvoltage Vpgm_reset can have a range of magnitudes as indicated by arrow404. The magnitude may be less than Vreset and then step up. Ireset is acurrent in the cell when it resets. Due to variations among cells, theywill set or reset under slightly different conditions. The use ofstep-wise increasing voltages allows each cell to set or reset using thelowest possible voltage.

FIG. 4B is a graph depicting I-V characteristics of an example bipolarresistance-switching material which sets using a negative voltage. Line400 represents the Rlow state and line 402 represents the Rhigh state asin FIG. 4A. Line 411 represents a reset and line 413 represents a set.Arrow 414 represents a range of magnitudes for Vpgm_set and arrow 415represents a range of magnitudes for Vpgm_reset.

FIG. 4C1 depicts a portion of the I-V plots of FIG. 4A or 4B showing theuse of a verify voltage of a stability verify test (Vver_stability)which is less than a verify voltage (Vread) of a program verify test, tomake the stability verify test more strict than the program verify testin a set process. A verify test for a set process can be made morestrict (harder to pass) by lowering the read voltage while fixing thereference current (Iverify_set). The figure indicates that a group ofmemory cells can vary in their I-V characteristic. Line 420 representsan upper bound of the group and line 421 represents a lower bound. Arrow422 denotes a range of current values for the group when Vread isapplied. The current values are all higher than Iverify_set so that averify test using Vread would pass for all of the cells in the group.Arrow 423 denotes a range of current values for the group whenVver_stability is applied. Some of the current values are lower thanIverify_set so that a verify test using Vver_stability would pass forsome but not all of the cells in the group.

The graphs are not necessarily to scale.

FIG. 4C2 depicts a portion of the I-V plots of FIG. 4A or 4B showing theuse of a verify voltage of a stability verify test (Vver_stability)which is more than a verify voltage (Vread) of a program verify test, tomake the stability verify test less strict than the program verify testin a set process. Arrow 450 denotes a range of current values for thegroup when Vver_stability is applied. All of the current values areabove Iverify_set so that a verify test using Vver_stability would passfor all of the cells in the group.

FIG. 4D depicts a portion of the I-V plots of FIG. 4A or 4B showing theuse of a verify current of a stability verify test (Iverify_set+ΔI)which is more than a verify current of a program verify test(Iverify_set), to make the stability verify test more strict than theprogram verify test in a set process, or the use of a verify current ofa stability verify test (Iverify_set−ΔI) which is less than a verifycurrent of a program verify test (Iverify_set), to make the stabilityverify test less strict than the program verify test in a set process.

A verify test for a set process can be made more strict by raising thereference current while fixing the read voltage. Arrow 424 denotes arange of current values for the set when Vread is applied. The currentvalues are all higher than Iverify_set so that a verify test usingIverify_set would pass for all of the cells in the group. However, thecurrent values are not all higher than Iverify_set+ΔI so that a verifytest using Iverify_set+ΔI would pass for some but not all of the cellsin the group.

Similarly, a verify test for a set process can be made less strict bylowering the reference current while fixing the read voltage. Thecurrent values are all higher than Iverify_set−ΔI so that a verify testusing Iverify_set−ΔI would pass for all of the cells in the group.

FIG. 4E1 depicts a portion of the I-V plots of FIG. 4A or 4B showing theuse of a verify voltage of a stability verify test (Vver_stability)which is more than a verify voltage (Vread) of a program verify test, tomake the stability verify test more strict than the program verify testin a reset process. A verify test for a reset process can be made morestrict by raising the read voltage while fixing the reference current(Iverify_set). Line 430 represents an upper bound of the group and line431 represents a lower bound. Arrow 433 denotes a range of currentvalues for the group when Vread is applied. The current values are alllower than Iverify_set so that a verify test using Vread would pass forall of the cells in the group. Arrow 432 denotes a range of currentvalues for the group when Vver_stability is applied. Some of the currentvalues are greater than Iverify_set so that a verify test usingVver_stability would pass for some but not all of the cells in thegroup.

FIG. 4E2 depicts a portion of the I-V plots of FIG. 4A or 4B showing theuse of a verify voltage of a stability verify test (Vver_stability)which is less than a verify voltage (Vread) of a program verify test, tomake the stability verify test less strict than the program verify testin a reset process. Arrow 460 denotes a range of current values for thegroup when Vver_stability is applied. All of the current values are lessthan Iverify_set so that a verify test using Vver_stability would passfor all of the cells in the group.

FIG. 4F depicts a portion of the I-V plots of FIG. 4A or 4B showing theuse of a verify current of a stability verify test (Iverify_reset−ΔI)which is less than a verify current of a program verify test(Iverify_reset), to make the stability verify test more strict than theprogram verify test in a reset process, or the use of a verify currentof a stability verify test (Iverify_reset+ΔI) which is more than averify current of a program verify test (Iverify_reset), to make thestability verify test less strict than the program verify test in areset process. A verify test for a reset process can be made more strictby lowering the reference current while fixing the read voltage. Arrow434 denotes a range of current values for the set when Vread is applied.The current values are all lower than Iverify_reset so that a verifytest using Iverify_reset would pass for all of the cells in the group.However, the current values are not all lower than Iverify_set−ΔI sothat a verify test using Iverify_reset−ΔI would pass for some but notall of the cells in the group.

Similarly, a verify test for a reset process can be made less strict byraising the reference current while fixing the read voltage. The currentvalues are all lower than Iverify_set+ΔI so that a verify test usingIverify_set+ΔI would pass for all of the cells in the group.

FIG. 5 depicts an embodiment of a circuit for reading the state of amemory cell. A portion of a memory array includes memory cells 550, 552,554 and 556. Two of the many bit lines and two of the many word linesare depicted. Bit line 559 is coupled to cells 550 and 554, and bit line557 is coupled to cells 552 and 556. Bit line 559 is the selected bitline and may be at 2 V, for instance. Bit line 557 is an unselected bitline and may be at ground, for instance. Word line 547 is the selectedword line and may be at 0 V, for instance. Word line 549 is anunselected word line and may be at 2 V, for instance.

A read circuit for one of the bit lines 559 is depicted to be connectedto the bit line via transistor 558, which is controlled by a gatevoltage supplied by column decoder 312 in order to select or unselectthe corresponding bit line. Transistor 558 connects the bit line to aData bus 563. Write circuit 560 (which is part of system control logic330) is connected to the Data bus. Transistor 562 connects to the Databus and operates as a clamp device that is controlled by clamp controlcircuit 564 (which is part of system control logic 330). Transistor 562is also connected to a sense amp 566, which includes a data latch 568.The output of sense amp 566 is connected to a data out terminal (tosystem control logic 330, a controller and/or a host). Write circuit 560is also connected to the sense amp 566 and the data latch 568.

When attempting to read the state of the resistance-switching material,all word lines are first biased at Vread (e.g., approximately 2 V) andall bit lines are at ground. The selected word line is then pulled toground. For example, this discussion will assume that memory cell 550 isselected for reading. One or more selected bit lines 559 are pulled toVread through the data bus (by turning on transistor 558) and the clampdevice (transistor 562, which receives ˜2 V+Vth, the threshold voltageof the transistor 562). The clamp device's gate is above Vread butcontrolled to keep the bit line near Vread. In one approach, current ispulled by the selected memory cell 550 through transistor 562 from asense node in the sense amp. The sense node can receive a referencecurrent that is between a high-resistivity state current and alow-resistivity state current. The sense node moves corresponding to thecurrent difference between the cell current and the reference current.Sense amp 566 generates a data out signal by comparing the sensedvoltage to a reference read voltage. If the memory cell current islarger than the reference current, the memory cell is in thelow-resistivity state and the voltage at the sense node will be lowerthan the reference voltage. If the memory cell current is smaller thanthe reference current, the memory cell is in the high-resistivity stateand the voltage at the sense node will be higher than the referencevoltage. The output data signal from the sense amp 566 is latched indata latch 568.

Referring again to FIG. 4A, for example, while in the high-resistivitystate (line 402), if one or more voltages of the program voltage andsufficient current are applied, the resistance-switching material can beset (line 401) to the low-resistivity state (line 400). The voltage willremain somewhat constant and the current will increase towardIset_limit. Note that the first time the resistance-switching materialis set, Vf (the forming voltage) is needed to set the device. Afterthat, one or more voltages of Vpgm are sufficient to set the device. Theforming voltage Vf may be greater than Vset. While in thelow-resistivity state (line 400), if Vpgm<0 V is applied, theresistance-switching material can be reset to the high-resistivity state(line 402).

In one embodiment, Vset is approximately 7 V, Vreset is approximately −9V, Iset_limit is approximately 1 to 10 μA and Ireset could be as low as,e.g., 100 nA. These voltages and currents apply to the case of aresistance-switching material and a diode in series.

FIG. 6A depicts an example process for changing the resistance state ofa memory cell. As an overview, step 600 begins a programming operation(e.g., a set or reset). Step 601 performs a first programming phase.Step 602 performs a stability test phase. In response to the resultsfrom the stability test phase, one of two branches is followed. In onebranch, step 603 performs a second programming phase. In another branch,step 604 ends the programming operation. This process addresses some ofthe challenges mentioned at the outset, including how to determine if amemory cell is in a stable state. As mentioned, with low currentoperation and shorter voltage durations, there is a relatively greaterchance of the memory cell being in a less stable state. This processprovides a practical way to find weak memory cells (e.g., memory cellswhich have an unstable state) and to repair them so that the statebecomes more stable. Moreover, this can be done in a short amount oftime and without degrading strong memory cells (e.g., memory cells whichhave a stable state).

Optionally, a loop back from step 603 to step 602 can be provided for asecond stability test phase. This approach can provide an extra degreeof assurance of stability before the end of the program operation. Inaddition, the loop between 602 and 603 could continue for one or moretimes until the stability test phase confirms a stable state. Thisapproach provides additional programming if indicated to achieve theextra degree of assurance.

Another embodiment avoids a second stability test phase to save time butmay result in fewer stable cells. However, this situation can beacceptable when ECC is used.

FIG. 6B depicts example details of a first programming phase inaccordance with step 601 of FIG. 6A. Step 610 set initial values forparameters (e.g., voltage magnitude and/or duration and/or currentlimit) for the first programming phase. Step 612 applies a programvoltage across a memory cell in accordance with the parameters. Step 613performs a program verify test, e.g., a read operation in which Vread isapplied and the current through the cell is compared to Iverify_set orIverify_reset to determine whether the set or reset state, respectively,has been reached. Decision step 614 determines whether the programverify test has been passed. If the answer is “yes,” the stability testphase begins at step 615. If the answer is “no,” step 611 updates one ormore values for the parameters, such as by increasing the voltagemagnitude and/or duration and/or the current limit.

FIG. 6C depicts example details of a stability test phase in accordancewith step 602 of FIG. 6A. Step 620 sets initial values for theparameters (e.g., voltage magnitude and/or duration and/or currentlimit) for the stability test phase. In one approach, the voltage isweaker than the voltages in the first programming phase, e.g., in termsof magnitude and/or duration and/or the current limit is lower. Inanother approach, the voltage is the same as one of voltage voltages inthe first programming phase. Step 622 applies one or more disturbvoltages across the memory cell in accordance with the parameters. Step623 performs a stability verify test, e.g., a read operation in whichVver_stability is applied and the current through the cell is comparedto Iverify_set or Iverify_reset to determine whether the set or resetstate, respectively, has been reached. As discussed, Vver_stability canbe the same as or different than Vread and Iverify_set or Iverify_resetcan be the same as or different than the levels used during theprogramming phase.

Decision step 624 determines whether the stability verify test has beenpassed. If the answer is “yes,” the programming operation ends at step626. If the answer is “no,” step 625 begins the second programmingphase. In this example, one stability verify test is performed in thestability test phase.

Optionally, a loop back from step 625 to step 623 can be used to againperform the stability test to provide an extra degree of assurance ofstability.

FIG. 6D depicts alternative example details of a stability test phase inaccordance with step 602 of FIG. 6A. Step 630 sets initial values forthe parameters (e.g., voltage magnitude and/or duration and/or currentlimit) for the stability test phase. Step 632 applies one or moredisturb voltages across a memory cell in accordance with the parameters.Step 633 performs a stability verify test as discussed previously.Decision step 634 determines whether a number of the stabilityiterations is less than a threshold number. If the answer is “yes,”another iteration in the stability test phase is performed beginning atstep 631 where one or more values for the parameters are optionallyupdated. If the answer is “no,” step 635 counts a number of passes andfails of the stability verify test. Decision step 636 determines whetherthe number of passes is greater than a threshold number. If the answeris “yes,” the programming operation ends at step 638. If the answer is“no,” the second programming phase begins at step 637.

Optionally, a loop back from step 637 to step 633 can be used to againperform the stability verify test. This provides an extra degree ofassurance of stability.

FIG. 6E depicts example details of a second programming phase inaccordance with step 603 of FIG. 6A. Step 640 sets initial values forthe parameters (e.g., voltage magnitude and/or duration and/or currentlimit) for the second programming phase based on values in the firstprogramming phase. Step 642 applies a program voltage across a memorycell in accordance with the parameters. Step 643 performs a programverify test. Decision step 644 determines whether the program verifytest is passed. If the answer is “yes,” the programming operation endsat step 645. Optionally, an additional stability test phase can beperformed to provide an extra degree of stability.

If the answer is “no,” one or more values of the parameters are updatedat step 641 and a next iteration is performed.

In one approach, the second programming phase represents a continuationof the first programming phase. For example, if the magnitude of theprogram voltage is Vpgm3_set (see FIG. 7) in the last iteration of thefirst programming phase, the magnitude of the program voltage can beVpgm4_set (see FIG. 7) in the first iteration of the second programmingphase. In this pattern, the magnitude of the program voltage isincreased by a step size each time the program voltage is applied in thefirst programming phase, the initial voltage in the second programmingphase is increased by the step size compared to the last voltage in thefirst programming phase, and the subsequent voltage voltages in thesecond programming phase are increased by the step size. However, otheroptions are possible. In one option, the second programming phase uses adifferent step size than the first programming phase. In another option,the initial voltage in the second programming phase has a same magnitudecompared to the last voltage in the first programming phase.

In another approach, the program voltage duration is increased insteadof the magnitude (see FIG. 8). If the duration of the program voltage isΔt3 in the last iteration of the first programming phase, the durationof the program voltage can be Δt4 in the first iteration of the secondprogramming phase. In this pattern, the duration of the program voltageis increased by a time step each time the program voltage is applied inthe first programming phase, the duration of the initial voltage in thesecond programming phase is increased by the time step compared to thelast voltage in the first programming phase, and the durations of thesubsequent voltages in the second programming phase are increased by thetime step. In one option, the second programming phase uses a differenttime step size than the first programming phase. In another option, theinitial voltage in the second programming phase has a same durationcompared to the last voltage in the first programming phase.

The current limit could also be incremented higher as the magnitude orduration of each program voltage is incremented. Generally, combinationsof one or more of the program voltage magnitude, program voltageduration and the current limit can be incremented for each iteration inthe first and second programming phases.

The first and second programming phases may be limited to a maximumnumber of iterations such that the programming operation ends in errorif these phases end before the program verify test is passed.

Various examples of the above-mentioned processes are discussed next inconnection with FIGS. 7 to 13.

FIG. 6F depicts a comparative set operation which is concluded after aprogram verify test is passed. This example is consistent with FIG. 4B,where negative voltages are applied in a set process. A program voltage661 of magnitude Vpgm1_set is followed by a read voltage 664 ofmagnitude Vread. In this case, assume the program verify test is failed.Subsequently, a program voltage 662 of magnitude Vpgm2_set is followedby a read voltage 665 of magnitude Vread. In this case, assume theprogram verify test is again failed. Subsequently, a program voltage 663of magnitude Vpgm3_set is followed by a read voltage 666 of magnitudeVread. In this case, assume the program verify test is passed and theset operation is completed. Essentially, once the set target is reached,the set operation is completed with no consideration for the stabilityof the resulting resistance state.

FIG. 6G depicts a comparative reset operation which is concluded after aprogram verify test is passed. A program voltage 671 of magnitudeVpgm1_reset is followed by a read voltage 674 of magnitude Vread. Inthis case, assume the program verify test is failed. Subsequently, aprogram voltage 672 of magnitude Vpgm2_reset is followed by a readvoltage 675 of magnitude Vread. In this case, assume the program verifytest is again failed. Subsequently, a program voltage 673 of magnitudeVpgm3_reset is followed by a read voltage 676 of magnitude Vread. Inthis case, assume the program verify test is passed and the resetoperation is completed. Essentially, once the reset target is reached,the reset operation is completed.

The approach of FIGS. 6F and 6G uses a dual polarity algorithm in whichone polarity is used for all voltages in the set process and theopposite polarity is used for all voltages in the reset process.Further, there is a read operation relative to a set or reset current.If the target is not met, the magnitude and/or duration of the voltageis increased and another program iteration is performed. However, asdepicted in FIG. 6H, this approach can result in a significant portionof the memory cells relaxing away from the set or reset state.

FIG. 6H depicts a relaxation of resistance-switching memory cells fromthe set or reset state over a time period such as one minute. The x-axisdepicts time such as on the scale of one minute and the y-axis depicts aread current through the memory cell for a given Vread.

Ion indicates a current of the memory cell when it is in a lowresistance (on) state. An example current is 100 nA and an exampleresistance is 0.5 mega ohms with a read voltage of 2 V. For example, aset operation may be performed which causes a memory cell to transitionfrom a high resistance state to the low resistance state. With thepassage of time, the memory cells can relax back toward the highresistance state, such that the resistance increases as evidenced by thedecrease in the current (since I=Vread/R). Plot 682 depicts the meanrelaxation of a group of memory cells away from a high resistance stateas a comparative example. Plot 680 depicts an improved mean relaxationof a group of memory cells away from a high resistance state using thetechniques discussed herein.

Similarly, Ioff indicates a current of the memory cell when it is in ahigh resistance (off) state. An example current is 50 nA and an exampleresistance is 1-50 mega ohms with a read voltage of 2 V. For example, areset operation may be performed which causes a memory cell totransition from a low resistance state to the high resistance state.With the passage of time, the memory cells can relax back toward the lowresistance state, such that the resistance decreases as evidenced by theincrease in the current. Plot 684 depicts the mean relaxation of a groupof memory cells away from a low resistance state as a comparativeexample. Plot 686 depicts an improved mean relaxation of a group ofmemory cells away from a low resistance state using the techniquesdiscussed herein.

FIG. 7 depicts example voltages used in a set process, where a magnitudeof the program voltages increases in first and second programmingphases, two disturb voltages have a same polarity as the programvoltages and a read operation is performed after each of the two disturbvoltages. This example is consistent with FIG. 4B, where negativevoltages are applied in a set process. The programming operationincludes a first programming phase 700, a stability test phase 710 and asecond programming phase 720. In this example, the program voltagemagnitude increases in steps. The first programming phase thus includesthree program voltages, each followed by a read voltage. For example, aprogram voltage 701 of magnitude Vpgm1_set is followed by a read voltage704, a program voltage 702 of magnitude Vpgm2_set is followed by a readvoltage 705 and a program voltage 703 of magnitude Vpgm3_set is followedby a read voltage 706. A program verify test is performed when eachread/verify voltage is applied. In this example, the program verify testis passed with the read voltage 706.

For simplicity, in FIGS. 7 to 13, Vread<0 V so that it has the samepolarity as the program pulses. However, Vread can be in the directionof a forward bias of a diode or other steering element, if present, inthe cell to minimize the effect of the diode or steering element duringthe read process. Generally, set and/or reset pulses may be positive ornegative relative to the forward bias direction of the cell and Vreadmay have a same or opposite polarity as the set and/or reset pulses.

A voltage can be applied, e.g., as a pulse having a fixed amplitude oras a waveform having a varying amplitude.

The stability test phase includes two example disturb voltages 711 and712 followed by a read voltages 713 and 714, respectively, of thestability verify test. These disturb voltages have a similar magnitudeas the program voltage 703 but are weaker because they are shorter induration. Thus, these voltages will not have a strong programming effecton the memory cell. Instead, these voltages provide a disturbance whichindicates whether the memory cell is weak and therefore has a tendencyto relax back toward its pre-programmed state. As mentioned, the secondprogramming phase may be omitted when the stability verify test ispassed with the read voltage 713 or 714.

As an example, the second programming phase includes two programvoltages, each followed by a read voltage. For example, a programvoltage 721 of magnitude Vpgm4_set is followed by a read voltage 723,and a program voltage 722 of magnitude Vpgm5_set is followed by a readvoltage 724. A program verify test is performed when each read/verifyvoltage is applied. In this example, the program verify test is passedwith the read voltage 724 at which point the programming operation mayend, or optionally a second stability test phase can be performed, asdiscussed previously.

In this example, during the stability test phase, the stability verifytest is not performed until after two or more of the disturb voltagesare applied. In any of the embodiments, a stability verify test may beperformed after each of the disturb voltages are applied such as shown,e.g., in FIG. 9.

One approach sets an amplitude of an initial program voltage (Vpgm4_set)in the second programming phase based on an amplitude of a last programvoltage (Vpgm3_set) in the first programming phase. The one or moreprogram voltages in the second programming phase can have an increasedmagnitude and/or duration compared to the one or more program voltagesin the first programming phase.

This approach uses program voltages having a polarity in the setdirection where each program voltage is followed by a read/verify. Ifthe cell reaches the target, then one or more short disturb voltages andone or more read voltages are applied and the state of the cell isdetected with the read voltage applied. If a pass status is detectedwith the one or more read voltages applied, the set process isconcluded. If a pass status is not detected with the one or more readvoltages applied, we increase the voltage (or voltage width) and applyan additional voltage followed by a read in one or more iterations untilthe read passes or until a maximum allowable number of iterations areperformed. An analogous reset process can use program voltages having apolarity in the reset direction (see FIG. 13).

A line 722 represents a current limit Iset_limit which may be increasedin magnitude in the second programming phase. Alternatively, the setcurrent limit could be increased step wise with the increase in themagnitude of the program pulses.

FIG. 8 depicts example voltages used in a set process, where a magnitudeof the program voltages increases in first and second programmingphases, three disturb voltages have a same polarity as the programvoltages and a read operation is performed after the three disturbvoltages.

The programming operation includes a first programming phase 800, astability test phase 810 and a second programming phase 820. In thisexample, the program voltage duration instead of magnitude increases insteps. The magnitude is fixed at Vpgm_set. Optionally, both themagnitude and duration increase step wise. The first programming phasethus includes a program voltage 801 of duration Δt1 followed by a readvoltage 804, a program voltage 802 of duration Δt2 followed by a readvoltage 805 and a program voltage 803 of duration Δt3 followed by a readvoltage 806. A program verify test is performed when each read/verifyvoltage is applied. In this example, the program verify test is passedwith the read voltage 806.

The stability test phase includes three example disturb voltages 811,812 and 813 where voltage 813 in this example is followed by a readvoltage 814 of the stability verify test. Alternatively, each of thedisturb voltages 811, 812 and 813 can be followed by a respective readvoltage. These disturb voltages have a reduced magnitude compared to theprogram voltages 801-803 and are also shorter in duration. As before,these disturb voltages will not have a strong programming effect on thememory cell but provide a disturbance which indicates whether the memorycell is weak.

As an example, the second programming phase includes two programvoltages, each followed by a read voltage. For example, a programvoltage 821 of duration of duration Δt4 is followed by a read voltage823, and a program voltage 822 of duration of duration Δt5 is followedby a read voltage 824. A program verify test is performed when eachread/verify voltage is applied. In this example, the program verify testis passed with the read voltage 824 at which point the programmingoperation ends.

FIG. 9 depicts example voltages used in a set process, where a magnitudeof the program voltages increases in first and second programmingphases, two disturb voltages have a same polarity as the programvoltages and a read operation is performed after each of the two disturbvoltages.

As mentioned in connection with FIG. 6D, it is possible to perform thestability verify test multiple times during the stability test phase andto count a number of times the stability verify test is passed orfailed. Based on this, a decision can be made as to whether to end theprogramming operation or to begin the second programming phase.

The programming operation includes a first programming phase 900, astability test phase 910 and a second programming phase 920. In thisexample, the program voltage magnitude increases in steps and theduration of each voltage is fixed. The first programming phase thusincludes a program voltage 901 of magnitude Vpgm1_set followed by a readvoltage 904, a program voltage 902 of magnitude Vpgm2_set followed by aread voltage 905 and a program voltage 903 of magnitude Vpgm3_setfollowed by a read voltage 906. A program verify test is performed wheneach read/verify voltage is applied. In this example, the program verifytest is passed with the read voltage 906.

The stability test phase includes a first disturb voltage 911 followedby a read voltage 913, and a second voltage 912 followed by a readvoltage 914. The first and second voltages have a reduced durationcompared to the program voltages 901-903 and are similar in magnitude toVpgm3_set. As before, these disturb voltages will not have a strongprogramming effect on the memory cell but provide a disturbance whichindicates whether the memory cell is weak. Moreover, by performingmultiple stability verify tests in the stability test phase, a finergrained decision can be made as to whether the second programming phaseis warranted. For example, if neither of the two stability verify testsis passed, the second programming phase is warranted. If both of the twoverify tests are passed, the second programming phase is not warranted.If one of the two stability verify tests is passed (and the other isfailed), the second programming phase may or may not be warranted. Nrepresents a number of passes or fails. One approach is to perform thesecond programming phase to provide extra assurance that the memory cellis programmed to a stable state and will not relax out of that state.This second programming phase incurs additional programming time.Another option is to provide more emphasis on a faster programming time,in which case the second programming phase is not performed when one ofthe two stability verify tests is passed.

An even finer grained decision can be made as to whether the secondprogramming phase is warranted when more than two stability verify testsare performed in the stability test phase. For instance, the secondprogramming phase may be warranted when there are zero or one passes ofthe stability verify test, while the second programming phase may not bewarranted when there are two or three passes of the stability verifytest. In another possible approach, values for the parameters can be setbased on a result of the stability test phase.

In one approach, different stability tests are performed which havedegrees of strictness and a decision of whether the second programmingphase is warranted is based on the results of these tests. For example,if a less strict verify test is passed but a more strict verify test isfailed, the second programming phase may be warranted.

As an example, the second programming phase includes two programvoltages, each followed by a read voltage. For example, a programvoltage 921 of magnitude Vpgm4_set is followed by a read voltage 923,and a program voltage 922 of magnitude Vpgm5_set is followed by a readvoltage 924. A program verify test is performed when each read/verifyvoltage is applied. In this example, the program verify test is passedwith the read voltage 924 at which point the programming operation ends.

A further option is to set at least one of a magnitude, a duration, or acurrent limit in the second programming phase based on a number N>=1 oftimes the memory cell fails or passes the stability verify test duringthe stability test phase.

FIG. 10 depicts example voltages used in a set process, where amagnitude of the program voltages increases in first and secondprogramming phases, two disturb voltages have an opposite polarity asthe program voltages and a read operation is performed after the twodisturb voltages. This example is similar to the example of FIG. 7except the disturb voltages 1011 and 1012 have an opposite (positive)polarity compared to a polarity (negative) of the program voltages inthe first and second programming phases.

The programming operation includes a first programming phase 1000, astability test phase 1010 and a second programming phase 1020. The firstprogramming phase includes a program voltage 1001 of magnitude Vpgm1_setfollowed by a read voltage 1004, a program voltage 1002 of magnitude ΔVpgm2_set followed by a read voltage 1005 and a program voltage 1003 ofmagnitude Vpgm3_set followed by a read voltage 1006. A program verifytest is performed when each read/verify voltage is applied. The programverify test is passed with the read voltage 1006.

The stability test phase includes a first voltage 1011 and a secondvoltage 1012, both having a positive polarity, followed by a readvoltage 1013. Optionally, the first voltage can be followed by a readpulse as well. The first and second voltages have a reduced duration andamplitude compared to the program voltage 1003.

As an example, the second programming phase includes a program voltage1021 of magnitude Vpgm4_set followed by a read voltage 1023, and aprogram voltage 1022 of magnitude Vpgm5_set followed by a read voltage1024. A program verify test is performed when each read/verify voltageis applied. The program verify test is passed with the read voltage 1024at which point the programming operation ends.

FIG. 11 depicts example voltages used in a set process, where amagnitude of the program voltages increases in first and secondprogramming phases, two disturb voltages have different polarities and aread operation is performed after the two disturb voltages. This exampleis similar to the example of FIG. 10 except the disturb voltages 1111and 1112 have opposite polarities. Optionally, each disturb voltage canbe followed by a read pulse.

The programming operation includes a first programming phase 1100, astability test phase 1110 and a second programming phase 1120. The firstprogramming phase includes a program voltage 1101 of magnitude Vpgm1_setfollowed by a read voltage 1104, a program voltage 1102 of magnitude ΔVpgm2_set followed by a read voltage 1105 and a program voltage 1103 ofmagnitude Vpgm3_set followed by a read voltage 1106. A program verifytest is performed when each read/verify voltage is applied. The programverify test is passed with the read voltage 1106.

The stability test phase includes a first voltage 1111 having a positivepolarity and a second voltage 1112 having a negative polarity, followedby a read voltage 1113. The first and second voltages have a reducedduration and amplitude compared to the program voltage 1103.

As an example, the second programming phase includes a program voltage1121 of magnitude Vpgm4_set followed by a read voltage 1123, and aprogram voltage 1122 of magnitude Vpgm5_set followed by a read voltage1124. A program verify test is performed when each read/verify voltageis applied. The program verify test is passed with the read voltage 1124at which point the programming operation ends.

FIG. 12 depicts example voltages used in a set process, where amagnitude of the program voltages increases in first and secondprogramming phases, and two disturb voltages are additional programvoltages. In this case, the disturb voltages have a magnitude and/orduration which is comparable to the last program voltage 1203 of thefirst programming phase, for instance. Once the first programming phasehas been completed, one or more disturb voltages are applied and one ormore stability verify tests are performed in the stability test phase.Since the program voltages of the stability test phase provide aprogramming effect, a memory cell that fails one or both of the verifytests can be considered to be a weak cell which is highly subject torelaxing out of the programmed state and back toward its pre-programmedstate. In this case, the second programming phase is warranted.

The programming operation includes a first programming phase 1200, astability test phase 1210 and a second programming phase 1220. The firstprogramming phase includes a program voltage 1201 of magnitude Vpgm1_setfollowed by a read voltage 1204, a program voltage 1202 of magnitude ΔVpgm2_set followed by a read voltage 1205 and a program voltage 1203 ofmagnitude Vpgm3_set followed by a read voltage 1206. A program verifytest is performed when each read/verify voltage is applied. The programverify test is passed with the read voltage 1206.

The stability test phase includes a first voltage 1211 of magnitudeVpgm3_set followed by a read voltage 1213, and a second voltage 1212 ofmagnitude Vpgm3_set followed by a read voltage 1214.

The second programming phase includes a program voltage 1221 ofmagnitude Vpgm4_set followed by a read voltage 1223. A program verifytest is performed when each read/verify voltage is applied. The programverify test is passed with the read voltage 1223 at which point theprogramming operation ends.

FIG. 13 depicts example voltages used in a reset process. However, FIGS.7 to 13 are genially applicable to both set and/or reset processes. Amagnitude of the program voltages increases in first and secondprogramming phases, two disturb voltages have a same polarity as theprogram voltages and a read operation is performed after the seconddisturb voltage of the two disturb voltages. In this reset process,consistent with FIG. 4B, positive voltages are used for programming.This example is obtained by reversing the polarity of the voltages ofthe example of FIG. 7.

The programming operation includes a first programming phase 1300, astability test phase 1310 and a second programming phase 1320. The firstprogramming phase includes a program voltage 1301 of magnitudeVpgm1_reset followed by a read voltage 1304, a program voltage 1302 ofmagnitude Δ Vpgm2_reset followed by a read voltage 1305 and a programvoltage 1303 of magnitude Vpgm3_reset followed by a read voltage 1306.The program verify test is passed with the read voltage 1306.

The stability test phase includes a first disturb voltage 1311 and asecond disturb voltage 1312 followed by a read voltage 1313 in astability verify test. Optionally, each disturb voltage can be followedby a read pulse.

The second programming phase includes a program voltage 1321 ofmagnitude Vpgm4_reset followed by a read voltage 1323 and a programvoltage 1322 of magnitude Vpgm5_reset followed by a read voltage 1324. Aprogram verify test is performed when each read/verify voltage isapplied. The program verify test is passed with the read voltage 1324 atwhich point the programming operation ends.

Accordingly, it can be seen that, in one embodiment, a method isprovided for performing an operation to change a resistance state of amemory cell. The method includes: performing a first programming phaseby applying one or more program voltages to the memory cell until thememory cell passes a program verify test, the memory cell comprises aresistance-switching material; in response to the memory cell passingthe program verify test in the first programming phase, performing astability test phase by applying one or more disturb voltages to thememory cell and performing a stability verify test for the memory cell;determining whether further programming of the memory cell is warrantedbased on the stability test phase; and if further programming iswarranted based on the stability test phase, performing a secondprogramming phase by applying one or more program voltages to the memorycell.

In another embodiment, a memory device comprises: a resistance switchingmaterial between first and second electrodes; a first control lineconnected to the first electrode;

a second control line connected to the second electrode; and a controlcircuit connected to the first and second control lines. The controlcircuit, to perform a first programming phase, applies one or moreprogram voltages to the resistance switching material until theresistance switching material passes a program verify test, in responseto the resistance switching material passing the program verify test inthe first programming phase, performs a stability test phase in whichone or more disturb voltages are applied to the resistance switchingmaterial and a stability verify test is performed for the resistanceswitching material.

In another embodiment, a method for performing an operation to change aresistance state of a memory cell includes: performing a firstprogramming phase by applying one or more program voltages to the memorycell until the memory cell passes a program verify test, the memory cellcomprises a resistance-switching material; in response to the memorycell passing the program verify test in the first programming phase,performing a stability test phase by applying multiple disturb voltagesto the memory cell and performing a stability verify test multiple timesfor the memory cell; determining a number of times the memory cellpasses the stability verify test in the stability test phase; based onthe number of times the memory cell passes the stability verify test inthe stability test phase, determining whether further programming of thememory cell is warranted; if further programming of the memory cell iswarranted, performing a second programming phase by applying one or moreprogram voltages to the memory cell and performing the program verifytest; and if further programming of the memory cell is not warranted,concluding the operation without performing the second programmingphase.

The foregoing detailed description of the technology herein has beenpresented for purposes of illustration and description. It is notintended to be exhaustive or to limit the technology to the precise formdisclosed. Many modifications and variations are possible in light ofthe above teaching. The described embodiments were chosen to bestexplain the principles of the technology and its practical applicationto thereby enable others skilled in the art to best utilize thetechnology in various embodiments and with various modifications as aresuited to the particular use contemplated. It is intended that the scopeof the technology be defined by the claims appended hereto.

What is claimed is:
 1. A method for performing an operation to change aresistance state of a memory cell, comprising: performing a firstprogramming phase by applying one or more program voltages to the memorycell until the memory cell passes a program verify test, the memory cellcomprises a resistance-switching material; in response to the memorycell passing the program verify test in the first programming phase,performing a stability test phase by applying one or more disturbvoltages to the memory cell and performing a stability verify test forthe memory cell; determining a number of times the memory cell passesthe stability verify test in the stability test phase; based on thenumber of times the memory cell passes the stability verify test is thestability test phases, determining whether further programming of thememory cell is warranted based on the stability test phase; and iffurther programming is warranted based on the stability test phase,performing a second programming phase by applying one or more programvoltages to the memory cell.
 2. The method of claim 1, wherein: duringthe stability test phase, the stability verify test is not performeduntil after two or more of the disturb voltages are applied.
 3. Themethod of claim 1, wherein: the one or more disturb voltages have atleast one of a reduced magnitude or a reduced duration compared to theone or more program voltages in the first programming phase.
 4. Themethod of claim 1, wherein: the one or more disturb voltages have a samepolarity compared to the one or more program voltages in the firstprogramming phase and the one or more program voltages in the secondprogramming phase.
 5. The method of claim 1, wherein: the one or moredisturb voltages have an opposite polarity compared to the one or moreprogram voltages in the first programming phase and the one or moreprogram voltages in the second programming phase.
 6. The method of claim1, wherein: the one or more program voltages in the second programmingphase have at least one of an increased magnitude or an increasedduration compared to the one or more program voltages in the firstprogramming phase.
 7. The method of claim 1, further comprising: settingan amplitude of an initial program voltage in the second programmingphase based on an amplitude of a last program voltage in the firstprogramming phase.
 8. The method of claim 1, further comprising: settinga duration of an initial program voltage in the second programming phasebased on a duration of a last program voltage in the first programmingphase.
 9. The method of claim 1, further comprising: setting a largercurrent limit in the second programming phase than in the firstprogramming phase.
 10. The method of claim 1, further comprising:setting at least one of a magnitude, a duration, or a current limit inthe second programming phase based on a number N>=1 of times the memorycell fails the stability verify test during the stability test phase.11. The method of claim 1, further comprising: determining if the memorycell passes the program verify test in the second programming phase; andif the memory cell passes the program verify test in the secondprogramming phase, concluding the operation.
 12. The method of claim 1,wherein: the further programming of the memory cell is not warrantedbased on the stability test phase if the memory cell passes thestability verify test during the stability test phase a specified numberof N>=1 times.
 13. The method of claim 1, wherein: the furtherprogramming of the memory cell is warranted based on the stability testphase if the memory cell does not pass the stability verify test duringthe stability test phase a specified number of N>=1 times.
 14. Themethod of claim 1, wherein: if further programming is not warrantedbased on the stability test phase, concluding the operation withoutperforming the second programming phase.
 15. The method of claim 1,further comprising: the further programming of the memory cell iswarranted based on the stability test phase if the memory cell fails thestability verify test during the stability test phase at least one timeout of N>=2 times the stability verify test is applied.
 16. The methodof claim 1, wherein: the stability verify test is less strict than theprogram verify test.
 17. A memory device, comprising: a resistanceswitching material between first and second electrodes; a first controlline connected to the first electrode; a second control line connectedto the second electrode; and a control circuit connected to the firstand second control lines, the control circuit, to perform a firstprogramming phase, is configured to: apply one or more program voltagesto the resistance switching material until the resistance switchingmaterial passes a program verify test, in response to the resistanceswitching material passing the program verify test in the firstprogramming phase, perform a stability test phase in which one or moredisturb voltages are applied to the resistance switching material and astability verify test is performed for the resistance switchingmaterial, determine a number of times the resistance switching materialpasses the stability verify test in the stability test phase, and basedon the number of times the resistance switching material passes thestability verify test in the stability test phase, determine whetherfurther programming of the resistance switching material is warranted.18. The memory device of claim 17, wherein: the one or more disturbvoltages have at least one of a reduced magnitude or a reduced durationcompared to the one or more program voltages in the first programmingphase.
 19. The memory device of claim 17, wherein: the control circuit,in response to the resistance switching material failing the stabilityverify test in the stability test phase, is configured to perform asecond programming phase in which the control circuit applies one ormore program voltages to the resistance switching material until theresistance switching material again passes the program verify test. 20.The memory device of claim 19, wherein: the one or more disturb voltageshave at least one of a reduced magnitude or a reduced duration comparedto the one or more program voltages in the first programming phase andthe one or more program voltages in the second programming phase. 21.The memory device of claim 17, wherein: the stability verify test isless strict than the program verify test.
 22. A method for performing anoperation to change a resistance state of a memory cell, comprising:performing a first programming phase by applying one or more programvoltages to the memory cell until the memory cell passes a programverify test, the memory cell comprises a resistance-switching material;in response to the memory cell passing the program verify test in thefirst programming phase, performing a stability test phase by applyingmultiple disturb voltages to the memory cell and performing a stabilityverify test multiple times for the memory cell; determining a number oftimes the memory cell passes the stability verify test in the stabilitytest phase; based on the number of times the memory cell passes thestability verify test in the stability test phase, determining whetherfurther programming of the memory cell is warranted; if furtherprogramming of the memory cell is warranted, performing a secondprogramming phase by applying one or more program voltages to the memorycell and performing the program verify test; and if further programmingof the memory cell is not warranted, concluding the operation withoutperforming the second programming phase.
 23. The method of claim 22,wherein: further programming of the memory cell is warranted if thememory cell fails the stability verify test at least one time out ofN>=2 times.
 24. The method of claim 22, wherein: the one or more disturbvoltages have at least one of a reduced magnitude or a reduced durationcompared to the one or more program voltages in the first programmingphase and the one or more program voltages in the second programmingphase.